Clock signals are square waves used for timing digital systems. Spurious phase modulation of clock signals can lead to problems in system operation. Therefore, it is useful to simulate this spurious modulation with a clock phase modulator to test system performance under stressed conditions.
One technique for phase modulation is illustrated in FIG. 1. A phase-locked loop (PLL) 10 includes a voltage-controlled oscillator (VCO) 12 that is locked to a carrier signal v.sub.c from an oscillator 14. A modulating signal v.sub.m added after a phase detector 16 causes the output signal v.sub.o to be phase-modulated.
One disadvantage of the PLL method is the limited dynamic range of the phase detector 16 and its possible non-linearity. This limits the amplitude of the phase modulation and may cause amplitude distortion. Another disadvantage is the limited frequency range of the closed-loop design and its likely non-flat frequency response. This limits the frequency of the phase modulation and possibly causes frequency distortion. A more thorough treatment of phase modulation using PLLs is discussed in Phase-Locked Loop Circuit Design, by D. H. Wolaver, Section 9-1 (Prentice-Hall, 1991).
Another known technique for phase modulation is a direct digital synthesizer (DDS) as shown in FIG. 2. A DDS 18 may have a numerical input N.sub.m that controls the phase of the output signal v.sub.o. At each pulse of a clock signal v.sub.c from an oscillator 19, a number N.sub.f is added to an accumulator 20, forming a number N.sub.p representing the phase. A number N.sub.m proportional to the phase modulation is added to N.sub.p at summer 22. The sum N.sub.p +N.sub.m serves as the address for a look-up table 24 that provides a number N.sub.s. N.sub.s is the value of a sine wave for the phase represented by the sum N.sub.p +N.sub.m. A digital-to-analog converter (DAC) 26 and a low-pass filter (LPF) 28 produce a sinusoidal voltage v.sub.o proportional to N.sub.s. The Stanford Telecommunications STEL-2173 device is an example of such a DDS.
A disadvantage of the DDS method is the complexity of the circuitry and its resulting high cost, especially for high-speed operation. In particular, the accumulator 20, the sine wave look-up table 24, and the DAC 26 each require large circuits. The size of the circuitry results in delays that slow the speed of operation. Therefore, high-speed operation requires expensive technology such as gallium arsenide semiconductors.